Conventional 3D integration processes utilize through-substrate-vias (TSV) as an alternative to wire bonds and flip chips, to allow chips to be stacked vertically. A TSV is a vertical electrical interconnect that passes through a device wafer or other semiconductor substrate, and is exposed from the back surface of the device wafer. The TSV facilitates electrical connections between two or more vertically stacked wafers and/or chips.
Such TSVs are typically filled by an electroplating process. For example, TSV copper interconnects are typically produced by etching a via through a device wafer, depositing an insulating dielectric layer and a barrier layer, depositing a copper seed layer, filling of the vias by copper electrodeposition, and removing the excess copper by chemical-mechanical planarization (CMP).
However, there is a problem with forming a TSV opening and interconnect on a semiconductor device that has undergone CMOS (complementary metal-oxide semiconductor) processing. Forming a TSV opening on a CMOS device at the backend of processing, requires establishing an electrical connection to existing features on the CMOS device. Conventional approaches for forming a TSV opening on the backside of a CMOS device wafer can land the TSV opening on a metal layer of a metallization structure of the device.
Typically, CMOS processing utilizes metallization layers composed of a metal layer (e.g., aluminum (Al), copper (Cu), etc.) situated between a barrier layer (e.g., titanium (Ti), titanium/titanium nitride (Ti/TiN), tantalum/tantalum nitride (Ta/TaN), etc.). Etching to form the TSV opening can expose the metal layer (e.g., aluminum, etc.) which may be incompatible with the chemistry used to fill the TSV opening.
Moreover, while titanium and titanium nitride are compatible with most plating chemistries, it is difficult to form a TSV opening that involves etching through backend layers of a CMOS device and finishing on a TiN layer to facilitate a plating process. Such a process requires a buried oxide (BOX) etch that stops on TiN. However, BOX etches generally provides poor selectivity of oxide (e.g., silicon oxide, SiO2) versus TiN.